1. Field of the Invention
The present invention generally relates to a semiconductor device fabrication method, and more particularly, to fabrication of a contact via plug after so-called borderless via etching during a fabrication process of a semiconductor device with multilevel interconnection.
2. Description of the Related Art
Along with miniaturization of semiconductor devices, borderless via/wiring structures are often employed in multilevel interconnections used to improve the degree of integration. A borderless via/wiring structure has an upper-layer or lower-layer wiring pattern that does not completely cover the contact surface of the metal contact plug connecting the upper and lower wiring patterns. In other words, the upper-layer wiring pattern or the lower-layer wiring pattern is laterally displaced along the substrate surface and only partially overlaps the contact surface of the metal plug. See, for example, Japanese Laid-open Patent Publication No. 2003-218117A. It can be said that because of with miniaturization of device structures, a borderless structure is inevitably produced due to mask misalignment or exposure misalignment within the margin.
FIG. 1A through FIG. 1C illustrate a conventional process for fabricating multilevel interconnections with a borderless via/wiring structure. In FIG. 1A, a first metal wiring (M1) 12 is located on a first interlevel dielectric layer (D1) 11 over a semiconductor substrate (not shown). The first metal wiring 12 is covered with a second interlevel dielectric layer (D2) 13, and a second metal wiring (M2) 16 is located over the second interlevel dielectric layer 13. A contact metal plug (P) 15 surrounded by a barrier metal 14 connects the first metal wiring 11 with the second metal wiring 16. The second metal wiring 16 does not completely cover, but partially overlaps the top surface of the metal plug 15. This structure is called a borderless via/wiring structure. The metal plug 15 and the second metal wiring 16 are covered with a third interlevel dielectric layer 17, and a resist mask (R) 18 defining a prescribed pattern is located over the third interlevel dielectric layer 17.
Then, as illustrated in FIG. 1B, a contact hole 19 is formed in the third interlevel dielectric layer 17 by etching so as to reach the second metal wiring 16. Because of the borderless via/wiring structure, the contact hole 19 further reaches the metal plug 15 with the second metal wiring 16 serving as a stopper. As a result, two different metals, e.g., aluminum (Al) of the second metal wiring 16 and tungsten (W) of the metal plug 15, are exposed in the contact hole 19.
After the contact hole 19 is formed, the resist mask 18 is removed by an ashing process. With the conventional method, plasma ashing is typically performed using oxygen O2 gas, or N2 added and/or CF4 added to oxygen gas, such as O2/N2 or O2/N2-H2/CF4. During the resist ashing, the top surface of the metal (tungsten) plug 15 revealed under the second metal wiring 16 is exposed to the ashing plasma in the contact hole 19. Consequently, electric charge is accumulated on the surface of the tungsten plug 15.
Then, the device is rinsed using an amine based solvent to remove the residual sediment, such as heavy metal materials, remaining after the ashing. This amine based wet process causes the charged surface of the tungsten plug 15 to be easily dissolved. As a result, a dissolved portion 20 (see FIG. 1C) is produced in the tungsten plug 15. Even after the contact hole 19 is filled with a metal material, the dissolved portion 20 remains as a void or a cavity, which prevents good electric contact between the upper and lower metal wirings 16 and 12. This means that the device quality is degraded.